1. Field of the Invention
The present invention relates in general to a circuit for generating a voltage for precharging a bit line or a data line of a semiconductor memory device, and more particularly to an improved precharge voltage generator for equalizing the bit line or the data line of the semiconductor memory device at a high speed to enhance the data access speed of the semiconductor memory device.
2. Description of the Prior Art
Generally, a precharge voltage generator charges a bit line or a data line of a semiconductor memory device before data is transferred in order to enhance the transfer speed of the data. To this end, the precharge voltage generator applies a precharge voltage to the bit line or the data line of the semiconductor memory device, the precharge voltage having a value corresponding to half that of a supply voltage, namely, (Vcc-Vss)/2.
The bit line or the data line of the semiconductor memory device is precharged with the precharge voltage of (Vcc-Vss)/2 from the precharge voltage generator in a standby mode. On the contrary, in an active mode, the bit line or the data line of the semiconductor memory device is maintained at a supply voltage Vcc or a ground voltage Vss by a sense amplifier which senses and amplifies bit data from a memory cell array. When the semiconductor memory device is changed from the active mode to the standby mode, the supply voltage Vcc or the ground voltage Vss on the bit line or the data line of the semiconductor memory device must be recovered to the precharge voltage of (Vcc-Vss)/2 as soon as possible.
However, such a conventional precharge voltage generator is desirable to regulate the level of the precharge voltage with a variation in the level of the supply voltage, but has a disadvantage in that it has no function of adjusting an amount of current as the semiconductor memory device is changed in mode, resulting in no improvement in the speed at which the supply voltage vcc or the ground voltage vss on the bit line or the data line of the semiconductor memory device is recovered to the precharge voltage of (Vcc-Vss)/2. For this reason, the semiconductor memory device cannot access the data at a high speed because of a long standby time between the data access modes. Such a problem with the conventional precharge voltage generator will hereinafter be described in detail with reference to FIG. 1.
Referring to FIG. 1, there is shown a circuit diagram of the conventional precharge voltage generator. As shown in this drawing, the conventional precharge voltage generator comprises a first voltage divider 10 for generating first and second divided-voltage signals, and a second voltage divider 12 for generating the precharge voltage in response to the first and second divided-voltage signals from the first voltage divider 10.
The first voltage divider 10 includes a first PMOS transistor. Q1 connected between a supply voltage source Vcc and a first node N1, a first NMOS transistor Q2 connected between the first node N1 and a second node N2, a second PMOS transistor Q3 connected between the second node N2 and a third node N3, and a second NMOS transistor Q4 connected between the third node N3 and a ground voltage source Vss. The first divided-voltage signal V.sub.D1 is generated at the first node N1 and has a voltage value determined by the following equation (1): EQU V.sub.D1 =(R.sub.Q2 +R.sub.Q3 +R.sub.Q4).times.Vcc/(R.sub.Q1 +R.sub.Q2 +R.sub.Q3 +R.sub.Q4) (1)
where, R.sub.Q1, R.sub.Q2, R.sub.Q3 and R.sub.Q4 are resistances of the first PMOS transistor Q1, the first NMOS transistor Q2, the second PMOS transistor Q3 and the second NMOS transistor Q4, respectively.
The second divided-voltage signal V.sub.D2 is generated at the third node N3 and has a voltage value determined by the following equation (2): EQU V.sub.D2 =R.sub.Q4 .times.Vcc/(R.sub.Q1 +R.sub.Q2 +R.sub.Q3 +R.sub.Q4)(2)
The first and second divided-voltage signals V.sub.D1 and V.sub.D2 are varied in level with a variation in a level of the supply voltage Vcc.
The second voltage divider 12 includes a third NMOS transistor Q5 connected between the supply voltage source Vcc and an output node N4, and a third PMOS transistor Q6 connected between the output node N4 and the ground voltage source Vss. The third NMOS transistor Q5 has a gate for inputting the first divided-voltage signal V.sub.D1 from the first node N1 and the third PMOS transistor Q6 has a gate for inputting the second divided voltage signal V.sub.D2 from the third node N3. The third NMOS transistor Q5 has a resistance which is gradually increased as the first divided-voltage signal V.sub.D1 from the first node N1 is reduced in level. On the contrary, the third PMOS transistor 06 has a resistance which is reduced as the second divided-voltage signal V.sub.D2 from the third node N3 is reduced in level. In result, the third NMOS transistor Q5 and the third PMOS transistor Q6 generate the precharge voltage of (Vcc-Vss)/2 which is increased or reduced in level as the supply voltage (vcc-Vss) is increased or reduced in level. The generated precharge voltage of (Vcc-Vss)/2 is outputted through the output node N4. As the supply voltage (Vcc-Vss) is varied in level, the precharge voltage of (Vcc-Vss)/2 is increased or reduced to have a value of half that of the supply voltage (vcc-Vss).
As mentioned above, the conventional precharge voltage generator has only the function of generating the precharge voltage having the value corresponding to half that of the supply voltage, regardless of the variation in the mode of the semiconductor memory device. For this reason, the conventional precharge voltage generator cannot adjust an amount of current as the semiconductor memory device is changed in mode. As a result, much time is required in recovering the supply voltage or the ground voltage on the bit line or the data line of the semiconductor memory device to the precharge voltage when the semiconductor memory device is changed from the active mode to the standby mode. This results in a degradation in the successive data access operation of the semiconductor memory device.